Cadence Design Systems Inc. (NASDAQ: CDNS) is deepening its collaboration with Samsung Foundry in a multi-year agreement aimed at accelerating the development of next-generation chips for artificial intelligence (AI), automotive systems, and high-speed connectivity.
The expanded partnership, announced Monday, includes broadening Cadence’s memory and interface IP portfolio across Samsung’s most advanced nodes—SF4X, SF5A, and SF2P—and integrating AI-driven design tools for faster system-on-chip (SoC), chiplet, and 3D-IC development. The move comes amid rising demand for high-performance, energy-efficient semiconductors in data-intensive applications.
“We’re delivering the technologies our mutual customers need to innovate and bring products to market faster,” said Boyd Phelps, senior vice president and general manager of Cadence’s Silicon Solutions Group. “Our expanded IP agreement strengthens a partnership that spans everything from subsystems to full chiplet solutions on Samsung Foundry platforms.”
The companies are targeting multiple high-growth areas. In automotive, advanced driver-assistance systems (ADAS) and electrification require increasingly complex semiconductor architectures. In AI and high-performance computing (HPC), demand is surging for fast memory, low latency interconnects, and power-efficient processing. Cadence’s updated IP offerings include LPDDR6/5X, GDDR7, DDR5, PCIe 6.0 and 5.0, CXL 3.2, and UCIe-SP 32G, aimed at these performance-driven markets.
Samsung, meanwhile, has certified Cadence’s full digital flow for its latest SF2P node, including support for Hyper Cell methodology and Local Layout Effect (LLE) 2.0 technologies. The company is also working with Cadence to enable analog IP migration from 4nm to 2nm—a key move to reduce development time while preserving design fidelity.
“Cadence’s digital tools and silicon solutions are fully certified for our latest process nodes,” said Hyung-Ock Kim, vice president and head of Samsung’s Foundry Design Technology Team. “Our joint efforts are enabling customers to scale efficiently across advanced nodes and new chip architectures.”
The collaboration also encompasses co-design methodologies for mmWave RF chip packaging, built on Samsung’s 14nm FinFET process. This includes a complete Front-End Module (FEM) and Antenna-in-Package (AiP) flow tailored for high-frequency wireless applications.
Power integrity and thermal performance remain focal points. The companies are applying Cadence’s Voltus InsightAI and 3D-IC tools across the design stack—from early exploration to final signoff. In a joint project on Samsung’s SF2 node, up to 90% of IR-drop violations were resolved without significant trade-offs in timing or power.
