S2C, MachineWare, and Andes Technology have jointly launched a RISC-V co-emulation solution designed to address the increasing complexity of RISC-V-based chip development. The solution combines MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA prototyping systems, and Andes’ high-performance AX46MPV RISC-V CPU core, providing a unified environment for hardware and software co-verification.
As RISC-V designs evolve toward high-performance, multi-core, and highly customized architectures, pre-silicon software development and system validation have become more challenging. The new co-emulation solution supports a “shift-left” verification strategy, enabling hardware and software teams to work in parallel. This approach reduces development cycles, minimizes project risk, and accelerates time-to-market for next-generation RISC-V chips.
MachineWare’s SIM-V virtual platform, built on SystemC TLM-2.0, delivers high-speed simulation and extensive extensibility. It integrates with third-party toolchains for debugging, testing, and coverage analysis. SIM-V provides instruction-accurate reference models that fully implement the AndeStar V5 Instruction Set Architecture, including the RISC-V Vector (V) extension. Using the SIM-V Extension API, designers can model, validate, and debug proprietary processor enhancements within a complete system simulation while maintaining detailed trace and introspection capabilities. Lukas Jünger, CEO of MachineWare, said, “Our customers need tools that accelerate development without compromising accuracy. This co-emulation solution enables hardware and software validation in parallel, reduces integration risks, and helps bring products to market faster than ever before.”
Andes Technology contributes its AX46MPV multicore processor, an 8-stage superscalar 64-bit RISC-V CPU supporting up to 16 cores. It features a multi-level cache hierarchy, a powerful Vector Processing Unit with up to 1024-bit VLEN, High-Bandwidth Vector Memory, and custom ISA extensions via Andes ACE. With full MMU support for Linux and flexible performance scaling, AX46MPV is suited for data center AI workloads, Linux-capable edge AI platforms, and performance-critical MPUs in storage, networking, and other high-performance applications. Dr. Charlie Su, President and CTO of Andes Technology, said, “Our RISC-V IP is valued for its performance, robustness, and customizability. Through collaboration with MachineWare and S2C, we enable customers to evaluate software impacts and co-optimize silicon architecture before committing to costly tapeouts.”
S2C bridges virtual simulation and physical hardware through its Genesis Architect and Prodigy FPGA prototyping systems. In this hybrid setup, CPU models run in SIM-V while peripheral subsystems execute on FPGA, connected via a high-speed transactional bridge. This configuration allows full software stacks—from bootloader to application—to run realistically, while retaining detailed debug visibility. Ying, VP of S2C, said, “Through co-emulation, our customers can accelerate time-to-market, reduce costs, and ensure software maturity. By combining cycle-accurate debugging with high-speed execution, we deliver practical shift-left solutions for the RISC-V ecosystem.”
The co-emulation solution supports multiple stages of RISC-V development, including pre-silicon software validation, hardware/software co-verification, system performance analysis, and custom ISA extension development.
