JEDEC Solid State Technology Association, the global standard-setting body for microelectronics, is moving closer to finalizing the SPHBM4 standard, a memory innovation designed to deliver the performance of HBM4 while simplifying design and reducing pin count. The new standard is expected to play a key role in AI accelerators, high-performance computing, and data center applications where speed and efficiency are critical.
SPHBM4 uses the same DRAM dies as conventional HBM4 but sits on a new interface base die that can be mounted on standard organic substrates, rather than silicon. By running at higher frequencies and using 4:1 serialization, SPHBM4 achieves the same data throughput as HBM4 with just 512 data signals instead of 2,048. This not only maintains high performance but also eases manufacturing by relaxing connection requirements.
The memory capacity per stack remains identical to HBM4, while the organic substrate layout allows longer channel lengths between the memory and the system-on-chip (SoC). This could make it possible to integrate more SPHBM stacks in a system, boosting total memory capacity.
“JEDEC members are actively shaping the standards that will define next-generation modules for use in AI data centers, driving innovation in infrastructure and performance,” said Mian Quddus, Chairman of the JEDEC Board of Directors.
While the standard is nearing completion, JEDEC notes that specifications are subject to change during development. Companies interested in early insights and pre-publication proposals are encouraged to join JEDEC as members.
