Microchip Technology Inc. (Nasdaq: MCHP) has unveiled the industry’s first PCIe Gen 6 switches built on a 3-nanometer process, a move aimed at addressing escalating data movement and latency challenges in artificial intelligence (AI) and high-performance computing (HPC) systems. The new Switchtec Gen 6 PCIe Switch family promises higher bandwidth, improved energy efficiency, and enhanced security to meet the connectivity demands of next-generation data centers.
The launch comes as data-intensive workloads driven by generative AI and large-scale cloud computing strain existing interconnect architectures. Previous PCIe generations often created bottlenecks as data moved between CPUs, GPUs, memory, and storage, leading to underutilized compute capacity. The PCIe 6.0 specification doubles the bandwidth of PCIe 5.0 to 64 giga transfers per second (GT/s) per lane, offering a faster data pipeline to keep AI accelerators and processors fully engaged.
Microchip’s Switchtec Gen 6 switches enable up to 160 lanes of PCIe connectivity and are designed to link CPUs, GPUs, SoCs, AI accelerators, and storage devices with ultra-low latency. The 3nm process node helps reduce power consumption while supporting dense, high-speed interconnects critical for scaling modern AI and cloud infrastructure.
“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit. “By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy-efficient switch we’ve ever produced.”
The Switchtec Gen 6 family also integrates advanced security features, including a hardware root of trust and secure boot mechanisms based on post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0. These safeguards aim to protect next-generation data centers from evolving cybersecurity threats while maintaining integrity across complex AI and cloud environments.
Beyond raw performance, the new switches introduce several design improvements aligned with the PCIe 6.0 specification. They operate in Flow Control Unit (FLIT) mode and incorporate Forward Error Correction (FEC) for more efficient, reliable data transfer—especially for small, latency-sensitive packets typical of AI workloads. These enhancements minimize signal degradation and ensure consistent throughput in large-scale GPU clusters and distributed computing environments.
Each switch supports up to 20 ports and 10 stacks, featuring hot- and surprise-plug controllers for flexible system configurations. The architecture includes Non-Transparent Bridging (NTB) to connect multiple host domains, multicast functionality for one-to-many data distribution, and advanced diagnostics and error containment tools. An integrated MIPS processor, bifurcation options at x8 and x16, and support for multiple I/O interfaces enable broad system compatibility.
Microchip is complementing the hardware with its ChipLink diagnostic suite, which provides graphical configuration, debug, and analysis tools through in-band PCIe or sideband connections like UART, TWI, and EJTAG. Developers can also leverage the PM61160-KIT Switchtec Gen 6 Evaluation Kit, which offers multiple interfaces for prototyping and system testing.
Samples of the Switchtec Gen 6 PCIe switches are now available to qualified customers.
